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Senior Architect, Hardware AcceleratorsSanta Clara, California, United States

Senior Architect, Hardware Accelerators

Santa Clara | California | United States

Central to our mission is a highly programmable chip with workload specific hardware accelerators. Your role will be to identify and define hardware accelerators along with design of all aspects of digital SoC design, focusing on micro architecture, RTL, verification, logic synthesis, and timing analysis to deliver a design meeting target power, performance and area goals.

Skills, Education, and Experience Required
BS and/or MS in Electrical Engineering or equivalent degree
10+ years of RTL design and/or architecture experience
Proven track record with the definition and development of complex SoCs
Knowledge of logic design principles along with timing and power implications
Strong knowledge of Verilog, System Verilog, Synthesis and Static Timing Analysis
Self-motivated and able to work effectively independently and in a team
Additional Success Factors
Understanding of compression (DEFLATE, LZS, Huffman Encoding, dedupe, etc.) or crypto algorithms (symmetric & asymmetric key algorithms) or SSL/TLS protocol is required
ASIC, SoC, processor, CPU, silicon, chip, architecture, design, verification, DEFLATE, LZS, gzip, data deduplication, Huffman Encoding, AES, RSA, SHA, HMAC, ECDH, ECDSA

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