Senior Engineer/Architect, Hardware Accelerators at Fungible
Santa Clara, CA, US
Central to our mission is a highly programmable chip with workload-specific hardware accelerators. Your role will be to identify and define hardware accelerators, as well as to design and implement significant portions of the associated software e.g. regex compiler, functional model, etc.

Skills, Education and Experience Required
BS in Computer Science or equivalent degree
5+ years experience with regular expression, parser, compression (Deflate, LZS, Huffman Encoding, dedup, etc.), or cryptographic algorithms (symmetric & asymmetric key algorithms, SSL/TLS protocol)
Strong algorithmic & data structure background
Architectural sense: performance vs storage tradeoff, performance vs compression ratio trade off, etc.
Ability to write correct C or C++ code quickly
Desire to push the state of the art
Self-motivated, independent, and proactive
Additional Success Factors
Experience with Embedded OS/Linux environment
Experience with networking & storage stack.
Experience with security functions related to deep packet inspection (IDS/IPS, AV,malware detection, etc.), protocol buffers, and JSON
Experience with emerging new loss less compression algorithms used in data centers
Startup experience
embedded, Linux, networking stack, storage stack, security, DPI, deep packet inspection, DFA, NFA, PCRE, POSIX, Deflate, LZS, dedup, Huffman encoding, SSL, TLS, DES, 3DES, AES, RSA, DSA, DH, MD5, SHA, HMAC